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1 ? hip6021 advanced pwm and triple linear power controller the hip6021 provides the power control and protection for four output voltages in high-p erformance, graphics intensive microprocessor and computer applications. the ic integrates a voltage-mode pwm controller and three linear controllers, as well as the monitoring and protection functions into a 28- pin soic package. the pwm controller regulates the microprocessor core voltage with a synchronous-rectified buck converter. the linear cont rollers regulate the computer system?s agp 1.5v or 3.3v bus power, the 1.5v gtl bus power, and the 1.8v power for the north/south bridge core voltage and/or cache memory circuits. the hip6021 includes an intel-compatible, ttl 5-input digital-to-analog converter (dac) that adjusts the core pwm output voltage from 1.3v dc to 2.05v dc in 0.05v steps and from 2.1v dc to 3.5v dc in 0.1v increments. the precis ion reference and voltage-mode control provide 1% static regulation. the agp bus power linear controller?s output (v out2 ) is user-selectable, through a ttl-compatible signal applied at the select pin, for levels of 1.5v or 3.3v with 3% accuracy. based on the status of the fix pin, the other two linear regulators provide either fixed output voltages of 1.5v 3% (v out3 ) and 1.8v 3% (v out4 ), or user-adjustable by means of an external resistor divider. all linear controllers can employ either n-channel mosfets or bipolar npns for the pass transistor. the hip6021 monitors all the output voltages. a single power good signal is issued when the core is within 10% of the dac setting and all other out puts are above their under- voltage levels. additional built-in over-voltage protection for the core output uses the lowe r mosfet to prevent output voltages above 115% of the dac setting. the pwm controller?s over-current functi on monitors the output current by using the voltage drop across the upper mosfet?s r ds(on) . applications motherboard power regulation for computers features provides 4 regulated voltages - microprocessor core, agp bus, memory, and gtl bus power drives n-channel mosfets linear regulator drives compatible with both mosfet and bipolar series pass transistors fixed or externally resistor-adjustable linear outputs (fix pin) simple single-loop control design - voltage-mode pwm control fast pwm converter transient response - high-bandwidth error amplifier - full 0% to 100% duty ratio excellent output voltage regulation - core pwm output: 1% over temperature - other outputs: 3% over temperature ttl-compatible 5-bit dac mi croprocessor core output voltage selection - wide range . . . . . . . . . . . . . . . . . . . 1.3v dc to 3.5v dc power-good output voltage monitor over-voltage and over-current fault monitors - switching regulator does not require extra current sensing element, uses mosfet?s r ds(on) small converter size - constant frequency operation - 200khz free-running oscillator; programmable from 50khz to over 1mhz - small external component count pb-free available (rohs compliant) pinout hip6021 (soic) top view ordering information part number temp. range ( o c) package pkg. dwg. # hip6021cb 0 to 70 28 ld soic m28.3 hip6021cbz (note) 0 to 70 28 ld soic (pb-free) m28.3 hip6021eval1 evaluation board add ?-t? suffix for tape and reel. note: intersil pb-free products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. drive2 fix vid4 vid3 vsen2 select ss fault/rt vsen4 vcc pgnd lgate phase drive3 comp gnd vaux drive4 ugate 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 pgood vid2 sd vsen1 vsen3 vid1 vid0 ocset fb data sheet march 8, 2005 fn4684.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 1999, 2005. all rights reserved
2 block diagram soft- start inhibit pwm comp1 error amp1 vcc pgood pwm1 gnd vsen1 ocset vid0 vid1 vid2 vid3 fb comp dacout ugate phase 200 a 28 a 4.5v + - + - + - + - vid4 lgate pgnd drive4 drive3 vsen3 + - drive2 fix vsen2 fault / rt + - + - + - 1.26v power-on reset (por) ttl d/a converter (dac) oscillator + - gate control vcc vcc vcc and fault logic ss 1.5v synch drive drive1 + - + + - under- voltage vsen4 linear fault ov luv oc1 - or 3.3v + - select + - vaux vaux x 0.75 x 0.75 x 1.10 x 0.90 x 1.15 sd hip6021
3 simplified power system diagram typical application pwm +5v in v out1 q1 q2 q3 v out2 q4 v out3 v out4 linear linear linear hip6021 controller controller controller controller +3.3v in q5 vid1 vid2 vid3 vid4 ss gnd vcc +5v in vid0 +12v in v out1 pgnd vsen1 pgood lgate ugate ocset phase q1 q2 powergood fb comp 1.3v to 3.5v select drive2 q3 vsen2 drive3 vsen3 vsen4 c out4 1.5v 1.8v c out3 c out2 c in c out1 q4 l out1 hip6021 v out2 v out3 v out4 1.5v or 3.3v fault / rt c ss q5 +3.3v in typedet l in drive4 vaux fix hip6021
4 absolute maximum ratings thermal information supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15v pgood, rt/fault, drive, phase, and gate voltage . . . . . . . . . . . . . . . gnd - 0.3v to v cc + 0.3v input, output or i/o voltage . . . . . . . . . . . . . . . . . . gnd -0.3v to 7v esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 operating conditions supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . +12v 10% ambient temperature range . . . . . . . . . . . . . . . . . . . . 0 o c to 70 o c junction temperature range . . . . . . . . . . . . . . . . . . . 0 o c to 125 o c thermal resistance (typical, note 1) ja ( o c/w) soic package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 maximum junction temperature (plastic package) . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in ?a bsolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mounted on an evaluation pc board in free air. electrical specifications recommended operating conditions, unless otherwise no ted. refer to block and simplified power system diagrams, and typical application schematic parameter symbol test conditions min typ max units vcc supply current nominal supply current i cc ugate, lgate, drive2, drive3, and drive4 open -9- ma power-on reset rising vcc threshold v ocset = 4.5v - - 10.4 v falling vcc threshold v ocset = 4.5v 8.2 - - v rising vaux threshold v ocset = 4.5v - 2.5 - v vaux threshold hysteresis v ocset = 4.5v - 0.5 - v rising v ocset threshold -1.26- v oscillator free running frequency f osc rt = open 185 200 215 khz total variation 6k ? < rt to gnd < 200k ? -15 - +15 % ramp amplitude ? v osc rt = open - 1.9 - v p-p dac and bandgap reference dac(vid0-vid4) input low voltage --0.8v dac(vid0-vid4) input high voltage 2.0 - - v dacout voltage accuracy -1.0 - +1.0 % bandgap reference voltage v bg - 1.265 - v bandgap reference tolerance -2.5 - +2.5 % linear regulators (out2, out3, and out4) regulation (all linears) -3- % vsen2 regulation voltage vreg 2 select < 0.8v - 1.5 - v vsen2 regulation voltage vreg 2 select > 2.0v - 3.3 - v vsen3 regulation voltage vreg 3 -1.5- v vsen4 regulation voltage vreg 4 -1.8- v under-voltage level (vsen/vreg) vsen uv vsen rising - 75 - % under-voltage hysteresis (vsen/vreg) vsen falling - 7 - % output drive current (all linears) vaux-v drive > 0.6v 20 40 - ma hip6021
5 synchronous pwm controller error amplifier dc gain -88- db gain-bandwidth product gbwp - 15 - mhz slew rate sr comp = 10pf - 6 - v/ s pwm controller gate driver ugate source i ugate vcc = 12v, v ugate = 6v - 1 - a ugate sink r ugate v gate-phase = 1v - 1.7 3.5 ? lgate source i lgate vcc = 12v, v lgate = 1v - 1 - a lgate sink r lgate v lgate = 1v - 1.4 3.0 ? protection vsen1 over-voltage (vsen1/dacout) vsen1 rising - 115 120 % fault sourcing current i ovp v fault/rt = 2.0v - 8.5 - ma ocset1 current source i ocset v ocset = 4.5v dc 170 200 230 a soft-start current i ss -28- a power good vsen1 upper threshold (vsen1/dacout) vsen1 rising 108 - 110 % vsen1 under-voltage (vsen1/dacout) vsen1 rising 92 - 94 % vsen1 hysteresis (vsen1/dacout) upper/lower threshold - 2 - % pgood voltage low v pgood i pgood = -4ma - - 0.8 v electrical specifications recommended operating conditions, unless otherwise no ted. refer to block and simplified power system diagrams, and typical application schematic (continued) parameter symbol test conditions min typ max units typical performance curves figure 1. r t resistance vs frequency figure 2. bias supply current vs frequency 10 100 1000 switching frequency (khz) resistance (k ? ) 10 100 1000 r t pullup to +12v r t pulldown to v ss 100 200 300 400 500 600 700 800 900 1000 i cc (ma) switching frequency (khz) 100 80 60 40 20 0 c = 660pf c = 1500pf c = 3600pf c = 4800pf c ugate1 = c ugate2 = c lgate1 = c vin = 5v vcc = 12v hip6021
6 functional pin descriptions vcc (pin 28) provide a 12v bias supply for the ic to this pin. this pin also provides the gate bias charge for all the mosfets controlled by the ic. the voltage at this pin is monitored for power-on reset (por) purposes. gnd (pin 17) signal ground for the ic. all voltage levels are measured with respect to this pin. pgnd (pin 24) this is the power ground connection. tie the synchronous pwm converter?s lower mosfet source to this pin. vaux (pin 16) this pin provides boost current for the linear regulators? output drives in the event bi polar npn transistors (instead of n-channel mosfets) are em ployed as pass elements. the voltage at this pin is monitored for power-on reset (por) purposes. ss (pin 12) connect a capacitor from this pin to ground. this capacitor, along with an internal 28 a current source, sets the soft-start interval of the converter. fault / rt (pin 13) this pin provides oscillator switching frequency adjustment. by placing a resistor (r t ) from this pin to gnd, the nominal 200khz switching frequency is increased according to the following equation: conversely, connecting a resistor from this pin to vcc reduces the switching frequency according to the following equation: nominally, the voltage at this pin is 1.26v. in the event of an over-voltage or over-current condition, this pin is internally pulled to vcc. pgood (pin 8) pgood is an open collector output used to indicate the status of the output voltages. this pin is pulled low when the synchronous regulator output is not within 10% of the dacout reference voltage or when any of the other outputs are below their under-voltage thresholds. the pgood output is open for ?11111? vid code. sd (pin 9) this pin shuts down all the outputs. a ttl-compatible, logic level high signal applied at this pin immediately discharges the soft-start capacitor, disabling all the outputs. dedicated internal circuitry insures the core output voltage does not go negative during this process. when re-enabled, the ic undergoes a new soft-start cycle. left open, this pin is pulled low by an internal pull-down resistor, enabling operation. fix (pin 2) grounding this pin bypasses the internal resistor dividers that set the output voltage of the 1.5v and 1.8v linear regulators. this way, the output voltage of the two regulators can be adjusted from 1.26v up to the input voltage (+3.3v or +5v) by way of an external resistor divider connected at the corresponding vsen pin. the ne w output voltage set by the external resistor divider can be determined using the following formula: where r out is the resistor connected from vsen to the output of the regulator, and r gnd is the resistor connected from vsen to ground. left open, the fix pin is pulled high, enabling fixed output voltage operation. vid0, vid1, vid2, vid3, vid4 (pins 7, 6, 5, 4 and 3) vid0-4 are the ttl-compatible input pins to the 5-bit dac. the logic states of these five pins program the internal voltage reference (dacout). the level of dacout sets the microprocessor core converter output voltage, as well as the coresponding pgood and ovp thresholds. ocset (pin 23) connect a resistor from this pin to the drain of the respective upper mosfet. this resistor, an internal 200 a current source, and the upper mosfet?s on-resistance set the converter over-current trip point. an over-current trip cycles the soft-start function. the voltage at this pin is monitored for power-on reset (por) purposes and pulling this pin low with an open drain device will shutdown the ic. phase (pin 26) connect the phase pin to the pwm converter?s upper mosfet source. this pin represents the gate drive return current path and is used to monitor the voltage drop across the upper mosfet for ov er-current protection. ugate (pin 27) connect ugate pin to the pwm converter?s upper mosfet gate. this pin provides the gat e drive for the upper mosfet. lgate (pin 25) connect lgate to the pwm converter?s lower mosfet gate. this pin provides the gate drive for the lower mosfet. comp and fb (pin 20, and 21) comp and fb are the available external pins of the pwm converter error amplifier. the fb pin is the inverting input of the fs 200khz 510 6 r t k ? () -------------------- - + (r t to gnd) fs 200khz 410 7 r t k ? () -------------------- - ? (r t to 12v) v out 1.265v 1 r out r gnd ---------------- - + ?? ?? ?? = hip6021
7 error amplifier. similarly, the comp pin is the error amplifier output. these pins are used to compensate the voltage-mode control feedback loop of the synchronous pwm converter. vsen1 (pin 22) this pin is connected to the pwm converter?s output voltage. the pgood and ovp comparator circuits use this signal to report output voltage status and for over- voltage protection. drive2 (pin 1) connect this pin to the gate of an external mosfet. this pin provides the drive for the agp regulator?s pass transistor. vsen2 (pin 10) connect this pin to the output of the agp linear regulator. the voltage at this pin is regulated to the level predetermined by the logic-level status of the select pin. this pin is also monitored for under-voltage events. select (pin 11) this pin determines the output voltage of the agp bus linear regulator. a low ttl input sets the output voltage to 1.5v, while a high input sets the output voltage to 3.3v. drive3 (pin 18) connect this pin to the gate of an external mosfet. this pin provides the drive for the 1.5v regulator?s pass transistor. vsen3 (pin 19) connect this pin to the output of the 1.5v linear regulator. this pin is monitored for under-voltage events. drive4 (pin 15) connect this pin to the gate of an external mosfet. this pin provides the drive for the 1.8v regulator?s pass transistor. vsen4 (pin 14) connect this pin to the output of the linear 1.8v regulator. this pin is monitored for undervoltage events. description operation the hip6021 monitors and pr ecisely controls 4 output voltage levels (refer to block and simplified power system diagrams, and typical app lication schematic). it is designed for microprocessor computer applications with 3.3v, 5v, and 12v bias input from an atx power supply. the ic has a synchronous pwm controller and three linear controllers. the pwm controller (pwm) is designed to regulate the microprocessor core voltage (v out1 ). pwm controller drives 2 mosfets (q1 and q2) in a synchronous-rectified buck converter configuration and regulates the microprocessor core voltage to a level programmed by the 5-bit digital-to-analog converter (dac). one of the linear controllers is designed to regulate the advanced graphics port (agp) bus voltage (v out2 ) to a digitally-programmable level of 1.5v or 3.3v. selection of either output voltage is achieved by applying the proper logic level at the select pin. the remaining two linear controllers supply the 1.5v gtl bus power (v out3 ) and the 1.8v memory power (v out4 ). all linear controllers are designed to employ an external pass transistor. initialization the hip6021 automatically initializes upon receipt of input power. special sequencing of the input supplies is not necessary. the power-on reset (por) function continually monitors the input supply voltages. the por monitors the bias voltage (+12v in ) at the vcc pin, the 5v input voltage (+5v in ) on the ocset pin, and the 3.3v input voltage (+3.3v in ) at the vaux pin. the normal level on ocset is equal to +5v in less a fixed voltage drop (see over-current protection). the por function in itiates soft-start operation after all supply voltages exceed their por thresholds. soft-start the por function initiates the soft-start sequence. initially, the voltage on the ss pin rapidly increases to approximately 1v (this minimizes the soft-start interval). then an internal 28 a current source charges an external capacitor (c ss ) on the ss pin to 4.5v. the pwm error amplifier reference input (+ terminal) and output (comp pin) are clamped to a level proportional to the ss pin voltage. as the ss pin voltage slews from 1v to 4v, the out put clamp allows generation of phase pulses of increasing width that charge the output capacitor(s). after the output voltage increases to approximately 70% of the set value, the reference input clamp slows the output voltage rate-of-rise and provides a smooth transition to the final set voltage. additionally, all linear regulators? reference inputs are clamped to a voltage proportional to the ss pin voltage. this method provides a rapid and controlled output voltage rise. figure 3 shows the soft-start sequence for the typical application. at t0 the ss voltage rapidly increases to approximately 1v. at t1, the ss pin and error amplifier output voltage reach the valley of the oscillator?s triangle wave. the oscillator?s triangular wave form is compared to the clamped error amplifier output voltage. as the ss pin voltage increases, the pulse-width on the phase pin increases. the interval of increasing pulse-width continues until each output reaches suff icient voltage to transfer control to the input reference cl amp. if we consider the 2.5v core output (v out1 ) in figure 3, this time occurs at t2. during the interval between t2 and t3, the error amplifier reference ramps to the final value and the converter regulates the output a voltage proportional to the ss pin voltage. at t3 the input clamp voltage exceeds the reference voltage and the output voltage is in regulation. the remaining outputs are also programmed to follow the ss pin voltage. the pgood si gnal toggles ?high? when all output voltage levels have exceeded their under-voltage levels. see the soft-start interval section under hip6021
8 applications guidelines for a procedure to determine the soft-start interval. fault protection all four outputs are monitored and protected against extreme overload. a sustained overload on any output or an over- voltage on v out1 output (vsen1) disa bles all outputs and drives the fault/rt pin to vcc. figure 4 shows a simplified schematic of the fault logic. an over-voltage detected on vsen1 immediately sets the fault latch. a sequence of three over-current fault signals also sets the fault latch. the ove r-current latch is set dependent upon the states of the over -current (oc), linear under- voltage (luv) and the soft-start signals. a window comparator monitors the ss pin and indicates when c ss is fully charged to 4v (up signal). an under-voltage on either linear output (vsen2, vsen3, or vsen4) is ignored until after the soft-start interval (t 4 in figure 3). this allows v out2 , v out3 , and v out4 to increase without fault at start- up. cycling the bias input voltage (+12v in on the vcc pin off then on) resets the counter and the fault latch. over-voltage protection during operation, a short on the upper mosfet of the pwm regulator (q1) causes v out1 to increase. when the output exceeds the over-voltage threshold of 115% of dacout, the over-voltage comparator trips to set the fault latch and turns q2 on. this blows the input fuse and reduces v out1 . the fault latch raises the fault/rt pin to vcc. a separate over-voltage circuit provides protection during the initial application of power. for voltages on the vcc pin below the power-on reset (and above ~4v), the output level is monitored for voltages above 1.3v. should vsen1 exceed this level, the lower mosfet, q2 is driven on. over-current protection all outputs are protected against excessive over-currents. the pwm controller uses the upper mosfet?s on-resistance, r ds(on) to monitor the curre nt for protection against shorted output. all lin ear controllers monitor their respective vsen pins for under-voltage events to protect against excessive currents. figure 5 illustrates the over-current protection with an overload on out1. the overload is applied at t0 and the current increases through the inductor (l out1 ). at time t1, the over-current comparator trips when the voltage across q1 (i d r ds(on) ) exceeds the level programmed by rocset. this inhibits all outputs, discharges the soft-start capacitor (c ss ) with a 10ma current sink, and increments the counter. c ss recharges at t2 and initiates a soft-start cycle with the error amplifiers clamped by soft-start. with out1 still overloaded, the inductor current increases to trip the over-current comparator. again, this inhibits all outputs, but the soft-start voltage continues increasing to 4v before discharging. the counter incr ements to 2. the soft-start cycle repeats at t3 and trips the over-current comparator. the ss pin voltage increases to 4v at t4 and the counter increments to 3. this sets the fault latch to disable the converter. the fault is reported on the fault/rt pin. the linear controllers operate in the same way as the pwm in response to over-current faults. the differentiating factor for the linear controllers is that they monitor the vsen pins for under-voltage events. should excessive currents cause the voltage at the vsen pins to fall below the linear under- voltage threshold, the luv signal sets the over-current latch if c ss is fully charged. blanking the luv signal during the c ss charge interval allows the linear outputs to build above the under-voltage threshold during normal operation. cycling the bias input power of f then on resets the counter and the fault latch. figure 3. soft-start interval 0v 0v 0v time pgood soft-start (1v/div) output (0.5v/div) voltages v out1 (dac = 2.5v) v out2 ( = 3.3v) v out4 ( = 1.8v) v out3 ( = 1.5v) t1 t2 t3 t0 t4 fault latch s r q por counter oc1 ov luv + - + - 0.15v 4v ss vcc fault r figure 4. fault logic - simplified schematic up over- current latch inhibit s r q hip6021
9 a resistor (r ocset ) programs the over-current trip level for the pwm converter. as shown in figure 6, the internal 200 a current sink, i ocset develops a voltage across r ocset (v set ) that is referenced to v in . the drive signal enables the over-current comparator (over- current). when the voltage across the upper mosfet (v ds ) exceeds v set , the over-current comparator trips to set the over-current latch. both v set and v ds are referenced to v in and a small capacitor across r ocset helps v ocset track the variations of v in due to mosfet switching. the over-current function will trip at a peak inductor current (i peak) determined by: the oc trip point varies with mosfet?s r ds(on) temperature variations. to avoid over-current tripping in the normal operating load range, determine the r ocset resistor from the equation above with: 1. the maximum r ds(on) at the highest junction temperature. 2. the minimum i ocset from the specification table. 3. determine i peak for i peak > i out(max) + ( ? i)/2, where ? i is the output inductor ripple current. for an equation for the ripple current see the section under component guidelines titled ?output inductor selection?. out1 voltage program the output voltage of the pwm converter is programmed to discrete levels between 1.3v dc and 3.5v dc . this output (out1) is designed to supply the core voltage of intel?s advanced microprocessors. the voltage identification (vid) pins program an internal voltage reference (dacout) with a ttl-compatible 5-bit digital-to-analog converter. the level of dacout also sets the pgood and ovp thresholds. table 1 specifies the dacout voltage for the different combinations of connections on the vid pins. the vid pins can be left open for a logic 1 input, because they are internally pulled up to an internal voltage of about 5v by a 10 a current source. changing the vid inputs during operation is not recommended and could toggle the pgood signal and exercise the over-voltage protection. ?11111? vid pin combination disables the ic and opens the pgood pin. inductor current soft-start 0a 0v 2v 4v figure 5. over-current operation time t1 t2 t3 t0 t4 fault/rt 0v 10v overload applied fault reported count = 1 count = 2 count = 3 i peak = i ocset r ocset r ds on () --------------------------------------------------- - ugate ocset phase over- current + - gate control vcc oc 200 a v ds i d v set r ocset v in = +5v over-current trip: i ocset + + figure 6. over-current detection pwm drive i d r ds on () i ocset r ocset > v ds v set > v phase v in v ds ? = v ocset v in v set ? = table 1. out1 voltage program pin name nominal dacout voltage vid4 vid3 vid2 vid1 vid0 011111.30 011101.35 011011.40 011001.45 010111.50 010101.55 010011.60 010001.65 001111.70 001101.75 001011.80 001001.85 000111.90 000101.95 000012.00 000002.05 11111 0 hip6021
10 out2 voltage selection the agp regulator output voltage is internally set to one of two discrete levels, based on the status of the select pin. select pin is internally pulled ?high?, such that left open, the agp output voltage is by def ault set to 3.3v. the other discrete setting available is 1.5v, which can be obtained by grounding the select pin using a jumper or another suitable method capable of sinking a few tens of microamperes. the status of the select pin cannot be changed during operation of the ic without immediately causing a fault condition. out3 and out4 voltage adjustability the gtl bus voltage (1.5v, out3) and the chip set and/or cache memory voltage (1.8v, out4) are internally set for simple, low-cost implementation in typical intel motherboard architectures. however, if different voltage settings are desired for these two outputs, the fix pin provides the necessary adaptability. left open (nc), this pin sets the fixed output voltages described above. grounding this pin allows both output voltages to be set by means of external resistor dividers as shown in figure 7. application guidelines soft-start interval initially, the soft-start functi on clamps the error amplifier?s output of the pwm converter. this generates phase pulses of increasing width that char ge the output capacitor(s). after the output voltage increases to approximately 70% of the set value, the reference input of the error amplifier is clamped to a voltage proportional to the ss pin voltage. the resulting output voltages start-up as shown in figure 3. the soft-start function controls the output voltage rate of rise to limit the current surge at start-up. the soft-start interval and the surge current are programmed by the soft-start capacitor, c ss . programming a faster soft-start interval increases the peak surge current. the peak surge current occurs during the initial output voltage rise to 70% of the set value. shutdown the hip6021 features a dedica ted shutdown pin (sd). a ttl-compatible, logic high signal applied to this pin shuts down (disables) all four outputs and discharges the soft-start capacitor. following a shutdown, a logic low signal re-enables the outputs through initiation of a new soft-start cycle. left open this pin will asses a logic low state, due to its internal pull-down resistor, thus enabling normal operation of all outputs. the pwm output does not switch until the soft-start voltage (v ss ) exceeds the oscillator?s valley voltage. the references on each linear?s error amplifier are clamped to the soft-start voltage. holding the ss pin low (with an open drain or collector signal) turns off all four regulators. the ?11111? vid code also shuts down the ic. 11110 2.1 11101 2.2 11100 2.3 11011 2.4 11010 2.5 11001 2.6 11000 2.7 10111 2.8 10110 2.9 10101 3.0 10100 3.1 10011 3.2 10010 3.3 10001 3.4 10000 3.5 note: 0 = connected to gnd, 1 = open or connected to 5v through pull-up resistors table 1. out1 voltage program (continued) pin name nominal dacout voltage vid4 vid3 vid2 vid1 vid0 drive3 vsen3 vsen4 c out4 c out3 q4 hip6021 v out3 v out4 q5 +3.3v in drive4 vaux fix r s3 r p3 r s4 r p4 v out v bg 1 r s r p -------- + ?? ?? ?? = figure 7. adjusting the output voltage of outputs 3 and 4 hip6021
11 layout considerations mosfets switch very fast and efficiently. the speed with which the current transitions from one device to another causes voltage spikes ac ross the interconnecting impedances and parasitic circuit elements. the voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device over-voltage stress. careful component layout and printed circuit design minimizes the voltage spikes in the converter. consider, as an example, the turn- off transition of the upper pwm mosfet. prior to turn-off, the upper mosfet was carrying the full load current. during the turn-off, current stops flowing in the upper mosfet and is picked up by the lower mosfet or schottky diode. any inductance in the switched current path generates a large voltage spike during the switching interval. careful component selection, tight layout of the critical components, and short, wide circuit traces minimize the magnitude of voltage spikes. see the application note antbd for evaluation board drawings of the component placement and printed circuit board. there are two sets of critical components in a dc-dc converter using a hip6020 controller. the switching power components are the most critical because they switch large amounts of energy, and as such, they tend to generate equally large amounts of nois e. the critical small signal components are those connected to sensitive nodes or those supplying critical bypass current. the power components and the controller ic should be placed first. locate the input capacitors, especially the high- frequency ceramic decoupling capacitors, close to the power switches. locate the output indu ctor and output capacitors between the mosfets and the load. locate the pwm controller close to the mosfets. the critical small signal components include the bypass capacitor for vcc and the soft-start capacitor, c ss . locate these components close to t heir connecting pins on the control ic. minimize any leakage current paths from ss node, since the internal current source is only 28 a. a multi-layer printed circui t board is recommended. figure 8shows the connections of th e critical components in the converter. note that the capacitors c in and c out each represent numerous physical capacitors. dedicate one solid layer for a ground plane and make all critical component ground connections with vias to this layer. dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. the power plane should support the input power and output power nodes. use copper filled polygons on the top and bottom circuit layers for the phase nodes, but do not unnecessarily oversize these particular islands. since the phase nodes are subjected to very high dv/dt voltages, the stray capacitor formed be tween these islands and the surrounding circuitry will tend to couple switching noise. use the remaining printed circuit layers for small signal wiring. the wiring traces from the control ic to the mosfet gate and source should be sized to carry 2a peak currents. pwm controller feedback compensation the pwm controller uses voltage-mode control for output regulation. this section highlights the design consideration for a pwm voltage-mode controller. apply the methods and considerations only to the pwm controller. figure 9 highlights the voltage-mode control loop for a synchronous-rectified buck converter. the output voltage (v out ) is regulated to the reference voltage level. the reference voltage level is the dac output voltage (dacout). the error amplifier (e rror amp) output (v e/a ) is compared with the oscillator (osc) triangular wave to provide a pulse- width modulated (pwm) wave with an amplitude of v in at the phase node. the pwm wave is smoothed by the output filter (l o and c o ). the modulator transfer function is the small-signal transfer function of v out /v e/a . this function is dominated by a dc gain, given by v in /v osc , and shaped by the output filter, with a double pole break frequency at f lc and a zero at f esr . modulator break frequency equations the compensation network consists of the error amplifier (internal to the hip6021) and the impedance networks z in and z fb . the goal of the compensation network is to provide a closed loop transfer function with high 0db crossing frequency (f 0db ) and adequate phase margin. phase margin is the difference between the closed loop phase at f 0db and 180 degrees. the equations below relate the compensation network?s poles, zeros and gain to the components (r1, r2, r3, c1, c2, and c3) in figure 8. use these guidelines for locating the poles and zeros of the compensation network: 1. pick gain (r2/r1) for desired converter bandwidth 2. place 1 st zero below filter?s double pole (~75% f lc ) 3. place 2 nd zero at filter?s double pole 4. place 1 st pole at the esr zero 5. place 2 nd pole at half the switching frequency 6. check gain against error amplifier?s open-loop gain 7. estimate phase margin - repeat if necessary f lc 1 2 l o c o --------------------------------------- - = f esr 1 2 esr c o ----------------------------------------- = hip6021
12 compensation break frequency equations figure 10 shows an asymptotic plot of the dc-dc converter?s gain vs. frequency. the actual modulator gain has a high gain peak dependent on the quality factor (q) of the output filter, which is not shown in figure 9. using the above guidelines should yield a compensation gain similar to the curve plotted. the open loop error amplifier gain bounds the compensation gain. check the compensation gain at f p2 with the capabilities of the error amplifier. the closed loop gain is constructed on the log-log graph of figure 10 by adding the modulator gain (in db) to the compensation gain (in db). this is equivalent to multiplying the modulator transfer functi on to the compensation transfer function and plotting the gain. the compensation gain uses external impedance networks z fb and z in to provide a stable, high bandwidth (bw) overall loop. a stable control loop has a gain crossing with -20db/decade slope and a phase margin greater than 45 degrees. include worst case component variations when determining phase margin. component select ion guidelines output capacitor selection the output capacitors for each output have unique requirements. in general, the output capacitors should be selected to meet the dynamic regulation requirements. additionally, the pwm converters require an output capacitor to filter the current ripple. the load transient for the microprocessor core requires high quality capacitors to supply the high slew rate (di/dt) current demands. figure 8. printed circuit board power planes and islands v out1 q1 q2 q3 q4 c ss +12v c vcc via connection to ground plane island on power plane layer island on circuit plane layer l out1 c out1 cr1 hip6021 c in c out2 v out2 v out3 +5v in ss pgnd lgate1 ugate1 phase1 drive3 key gnd vcc drive2 ocset1 r ocset1 c ocset1 load v out4 drive4 +3.3v in l in q5 c out3 c out4 load load load +3.3v in figure 9. voltage-mode buck converter compensation design v out osc reference l o c o esr v in ? v osc error amp pwm driver (parasitic) z fb + - dacout r1 r3 r2 c3 c2 c1 comp v out fb z fb hip6021 z in comp driver detailed compensation components phase v e/a + - + - z in f z1 1 2 r 2c1 ----------------------------------- = f z2 1 2 r1 r3 + () c3 ------------------------------------------------------ - = f p1 1 2 r 2 c1 c2 c1 c2 + ---------------------- ?? ?? ------------------------------------------------------- = f p2 1 2 r 3c3 ----------------------------------- = figure 10. asymptotic bode plot of converter gain 100 80 60 40 20 0 -20 -40 -60 f p1 f z2 10m 1m 100k 10k 1k 100 10 open loop error amp gain f z1 f p2 f lc f esr compensation gain (db) frequency (hz) gain modulator gain closed loop gain 20 v in v pp ------------ ?? ?? ?? log 20 r2 r1 ------- - ?? ?? log hip6021
13 pwm output capacitors modern microprocessors produce transient load rates above 1a/ns. high frequency capacitors initially supply the transient current and slow the load rate-of-change seen by the bulk capacitors. the bulk filter capacitor values are generally determined by the esr (effective series resistance) and voltage rating requirements rath er than actual capacitance requirements. high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulne ss of these low inductance components. consult with the manufacturer of the load on specific decoupling requirements. use only specialized low-esr capacitors intended for switching-regulator applications for the bulk capacitors. the bulk capacitor?s esr determines the output ripple voltage and the initial voltage drop following a high slew-rate transient?s edge. an aluminum electrolytic capacitor?s esr value is related to the case size with lower esr available in larger case sizes. however, the equivalent series inductance (esl) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. unfortunat ely, esl is not a specified parameter. work with your ca pacitor supplier and measure the capacitor?s impedance with frequency to select a suitable component. in most cases, multip le electrolytic capacitors of small case size perform bette r than a single large case capacitor. linear output capacitors the output capacitors for the linear regulators provide dynamic load current. the linear controllers use dominant pole compensation integrated into the error amplifier and are insensitive to output capacitor selection. output capacitors should be selected for transient load regulation. pwm output inductor selection the pwm converter requires an output inductor. the output inductor is selected to meet the output voltage ripple requirements and sets the converter?s response time to a load transient. the inductor value determines the converter?s ripple current and the ripple voltage is a function of the ripple current. the ripple voltage and current are approximated by the following equations: increasing the value of inductance reduces the ripple current and voltage. however, the large inductance values increase the converter?s response time to a load transient. one of the parameters limiting the converter?s response to a load transient is the time re quired to change the inductor current. given a sufficiently fast control loop design, the hip6021 will provide either 0% or 100% duty cycle in response to a load transient. the response time is the time interval required to slew the inductor current from an initial current value to the post-transi ent current level. during this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor(s). minimizing the response time can minimize the output capacitance required. the response time to a transient is different for the application of load and the removal of load. the following equations give the approximate response time interval for application and removal of a transient load: where: i tran is the transient load current step, t rise is the response time to the application of load, and t fall is the response time to the removal of load. be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. input capacitor selection the important parameters for th e bulk input capacitors are the voltage rating and the rms current rating. for reliable operation, select bulk input capacitors with voltage and current ratings above the maximum input voltage and largest rms current required by the circuit. the capacitor voltage rating should be at least 1. 25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. the rms current rating requirement for the input capacitor of a buck regulator is approximately 1/2 of the summation of the dc load current. use a mix of input bypass capacitors to control the voltage overshoot across the mosfets. use ceramic capacitance for the high frequency decoupling and bulk capacitors to supply the rms current. small ceramic capacitors can be placed very close to the upper mosfet to suppress the voltage induced in the parasitic circuit impedances. for a through-hole design, several electrolytic capacitors (panasonic hfq series or nichicon pl series or sanyo mv-gx or equivalent) may be needed. for surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. these capacitors must be capable of handling the surge-current at power-up. the tps series available from avx, and the 593d series from sprague are both surge current tested. mosfet selection/considerations the hip6021 requires 5 external transistors. two n-channel mosfets are used in the synchronous-rectified buck topology of pwm1 converter. it is recommended that the agp linear regulator pass element be a n-channel mosfet as well. the gtl and memory linear controllers can also ? i v in v out ? f s l ------------------------------- - v out v in --------------- - = v out ? i ? esr = t rise l o i tran v in v out ? ------------------------------- - = t fall l o i tran v out ------------------------------ - = hip6021
14 each drive a mosfet or a npn bipolar as a pass transistor. all these transistors should be selected based upon r ds(on) , current gain, saturation voltages, gate supply requirements, and thermal management considerations. pwm mosfet selection and considerations in high-current pwm applications, the mosfet power dissipation, package selection and heatsink are the dominant design factors. the power dissipation includes two loss components; conduction loss and switching loss. these losses are distributed between the upper and lower mosfets according to duty factor (see the equations below). the conduction losses are the main component of power dissipation for the lower mosfets. only the upper mosfet has significant switching losses, since the lower device turns on and off into near zero voltage. the equations below assume linear voltage-current transitions and do not model power loss due to the reverse- recovery of the lower mosfet?s body diode. the gate- charge losses are dissipated by the hip6021 and don't heat the mosfets. however, large gate-charge increases the switching time, t sw which increases the upper mosfet switching losses. ensure that both mosfets are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. a separate heatsink may be necessary depending upon mosfet power, package type, ambient temperature and air flow. the r ds(on) is different for the two equations above even if the same device is used for both. this is because the gate drive applied to the upper mosfet is different than the lower mosfet. figure 11 shows the gate drive where the upper mosfet?s gate-to-source voltage is approximately vcc less the input supply. for +5v main power and +12vdc for the bias, the gate-to-source voltage of q1 is 7v. the lower gate drive voltage is +12vdc. a logic-level mosfet is a good choice for q1 and a logic-level mosfet can be used for q2 if its absolute gate-t o-source voltage rating exceeds the maximum voltage applied to vcc. rectifier cr1 is a clamp that catches the negative inductor swing during the dead time between the turn off of the lower mosfet and the turn on of the upper mosfet. the diode must be a schottky type to prevent the lossy parasitic mosfet body diode from conducting. it is acceptable to omit the diode and let the bod y diode of the lower mosfet clamp the negative inductor swing, but efficiency could drop one or two percent as a resu lt. the diode's rated reverse breakdown voltage must be greater than the maximum input voltage. linear controller transistor selection the main criteria for selection of transistors for the linear regulators is package selection for efficient removal of heat. the power dissipated in a linear regulator is: select a package and heatsink that maintains the junction temperature below the rating with a the maximum expected ambient temperature. when selecting bipolar npn transistors for use with the linear controllers, insure the current gain at the given operating vce is sufficiently large to provide the desired output load current when the base is fed with the minimum driver output current. p upper i o 2 r ds on () v out v in ------------------------------------------------------------ i o v in t sw f s 2 ---------------------------------------------------- + = p lower i o 2 r ds on () v in v out ? () v in -------------------------------------------------------------------------------- - = figure 11. upper gate drive - direct v cc drive option +12v pgnd hip6021 gnd lgate ugate phase vcc +5v or less note: note: v gs v cc q1 q2 + - v gs v cc -5v cr1 p linear i o v in v out ? () = hip6021
15 all intersil u.s. products are manufactured, asse mbled and tested utilizin g iso9000 quality systems. intersil corporation?s quality certifications c an be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com hip6021 dc-dc converte r application circuit figure 12 shows an application circuit of a power supply for a microprocessor computer system . the power supply provides the microprocessor core voltage (vout1), the agp bus voltage (vout2), the gtl bus voltage (vout3), and the memory voltage (vout4) from +3.3v, +5vdc, and +12vdc. for detailed information on the circuit, including a bill-of-materials and circuit board description, see application note an9836. also see intersil?s web page (http://www.intersil.com). vid1 vid2 vid3 vid4 ss gnd vcc +5v in vid0 +12v in pgnd vsen1 pgood lgate ugate ocset phase q1,2 powergood fb comp v out2 vsen2 drive2 q3 drive3 vsen3 drive4 c25,26 v out3 v out4 c23,24 c12-19 hip6021 q4 l2 + + + + + c7 l1 c1-6 c9 c8 r1 v out1 r2 r3 c20 c21 c22 c27 2x1000 f 2x1000 f c10,11 2x1000 f 1 h 6x1000 f 1 f 1 f 1000pf 8x1000 f 0.1 f 4.2 h 0.22 f 10pf 2.7nf 10.2k 1.62k gnd (3.3v or 1.5v) (1.5v) (1.8v) vsen4 typedet select +3.3v in r5 499k r4 150k sd fix 1.0k q5 u1 1 2 3 4 5 6 7 8 9 10 11 12 13 16 15 14 17 18 19 20 21 22 23 24 25 26 27 28 fault/rt vaux huf76107d3s huf76107d3s huf76121d3s 2xhuf76143s3s (1.3v-3.5v) figure 12. power supply application circuit for a microprocessor computer system hip6021
hip6021 printer friendly version advanced pwm and triple linear power controller datasheets, related docs & simulations description key features parametric data related devices ordering information part no. design-in status temp. package msl price us $ hip6021cb active comm 28 ld soic 2 3.25 hip6021cb-t active comm 28 ld soic t+r 2 3.25 hip6021cbz active comm 28 ld soic 3 3.25 HIP6021CBZ-T active comm 28 ld soic t+r 3 3.25 hip6021eval1 active eval board n/a hip6021cbza inactive comm 28 ld soic 3 hip6021cbza-t inactive comm 28 ld soic t+r 3 the price listed is the manufacturer's suggested retail price for quantities between 100 and 999 units. however, prices in today's market are fluid and may change without notice. msl = moisture sensitivity level - per ipc/jedec j-std-020 smd = standard microcircuit drawing description the hip6021 provides the power control and protection for four output voltages in high- performance, graphics intensive microprocessor and computer applications. the ic integrates a voltage-mode pwm controller and three linear controllers, as well as the monitoring and protection functions into a 28- pin soic package. the pwm controller regulates the microprocessor core voltage with a synchronous-rectified buck converter. the linear controllers regulate the computer system?s agp 1.5v or 3.3v bus power, the 1.5v gtl bus power, and the 1.8v power for the north/south bridge core voltage and/or cache memory circuits. the hip6021 includes an intel- compatible, ttl 5-input digital-to-analog converter (dac) that adjusts the core pwm output voltage from 1.3v dc to 2.05v dc in 0.05v steps and from 2.1v dc to 3.5v dc in 0.1v increments. the precision reference and voltage-mode control provide 1% static regulation. the agp bus power linear controller?s output (v out2 ) is user-selectable, through a ttl-compatible signal applied at the select pin, for levels of 1.5v or 3.3v with 3% accuracy. based on the status of the fix pin, the other two linear regulators provide either fixed output voltages of 1.5v3% (v out3 ) and 1.8v3% (v out4 ), or user-adjustable by means of an external resistor divider. all linear controllers can employ either n-channel mosfets or bipolar npns for the pass transistor. the hip6021 monitors all the output voltages. a single power good signal is issued when the core is within 10% of the dac setting and all other outputs are above their undervoltage levels. additional built-in over-voltage protection for the core output uses the lower mosfet to prevent output voltages above 115% of the dac setting. the pwm controller?s over-current function monitors the output current by using the voltage drop across the upper mosfet?s r ds(on) . key f eatures provides 4 regulated voltages microprocessor core, agp bus, memory, and gtl bus power drives n-channel mosfets linear regulator drives compatible with both mosfet and bipolar series pass transistors fixed or externally resistor-adjustable linear outputs (fix pin) simple single-loop control design voltage-mode pwm control fast pwm converter transient response high-bandwidth error amplifier full 0% to 100% duty ratio
excellent output voltage regulation core pwm output: 1% over temperature other outputs: 3% over temperature ttl-compatible 5-bit dac microprocessor core output voltage selection wide range 1.3v dc to 3.5v dc power-good output voltage monitor over-voltage and over-current fault monitors switching regulator does not require extra current sensing element, uses mosfet?s r ds(on) small converter size constant frequency operation 200khz free-running oscillator; programmable from 50khz to over 1mhz small external component count pb-free available (rohs compliant) related documentation application note(s): motherboard power conversion solutions using the hip6020 and hip6021 controller ics datasheet(s): advanced pwm and triple linear power controller parametric data v in (min) (v) 5 v in (max) (v) 5 v out1 (min) (v) 1.3 v out1 (max) (v) 3.5 v out2 (v) 1.5 or 3.3 (also adj. higher) v out3 (v) 1.5 (also adj. higher) v out4 (v) 1.8 (also adj. higher) i out1 (a) 25 related devices parametric table hip6019b advanced dual pwm and dual linear power control hip6521 pwm and triple linear power controller isl6232 high efficiency system power supply controller for notebook computers isl6236 high-efficiency, quad-output, main power supply controllers for notebook computers isl6236a high-efficiency, quad-output, main power supply controllers for notebook computers isl6432 pwm and triple linear power controller for home gateway applications isl6521 pwm buck dc/dc and triple linear power controller isl6523 vrm8.5 dual pwm and dual linear power system controller isl6524 vrm8.5 pwm and triple linear power system controller isl6524a vrm8.5 pwm and triple linear power system controller isl6537 acpi regulator/controller for dual channel ddr memory systems isl6548 acpi regulator/controller for dual channel ddr memory systems about us | careers | contact us | investors | legal | privacy | site map | subscribe | intranet ?2007. all rights reserved.

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